In most real signal transmission applications there can be several sources of noise and distortions between the source of the signal and its receiver. As a result, there is a strong need to correct mistakes in the received signal. As a solution for this task one should use some coding technique with adding some additional information (i.e., additional bits to the source signal) to ensure correcting errors in the output distorted signal and decoding it. One type of coding technique utilizes low-density parity-check (LDPC) codes. LDPC codes are used because of their fast decoding (linearly depending on codeword length) property.
LDPC decoders correct errors by unsatisfied checks. When the number of unsatisfied check is low, decoders tends to keep the errors and fall into “trapping sets,” or stable configurations that may not be resolved by further decoding iterations. One mechanism for addressing this problem is targeted symbol flipping.
Targeted symbol flipping is the process of changing one or more variable bits associated with an unsatisfied check so that further decoding is possible. Targeted symbol flipping has long latency and complicated mode switching because memory elements send a request to get symbol addresses before each trial. Besides long runtimes, the hardware has a complicated state machine that is difficult to verify. Targeted symbol flipping as it exists currently has too many modes and suffers from long latency.
Consequently, it would be advantageous if an apparatus existed that is suitable for simplified targeted symbol flipping.